Product Design, Manufacturing & Innovation Resources

Últimas publicaciones y patentes sobre semiconductores

Semiconductores

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Esta es nuestra última selección de publicaciones y patentes mundiales en inglés sobre Semiconductores, entre muchas revistas científicas en línea, clasificadas y centradas en semiconductor, diodo, MOFSET, unión PN, tipo N, tipo P, BJT y JFET.

A laser scattering-based particulate counter sensor

Patent published on the 2026-10-15 in WO under Ref WO2026215919 by PATEL SOHIL [IN] (Patel Sohil [in])

Abstract: The present invention relates to a laser scattering-based particulate counter sensor for measuring particle size and concentration in an air sample The sensor comprises a laser diode, a light scattering cavity, a photodetector array, and an embedded processor. The sensor may further include environmental sensors and a dehumidification module to improve measurement accuracy under varying environmental conditions. The embedded processor may dynamically compensate for environmental effects, differe[...]


Our summary: A laser scattering-based particulate counter sensor measures particle size and concentration in air samples. It includes a laser diode, light scattering cavity, photodetector array, and an embedded processor for dynamic compensation. The sensor improves accuracy in high-humidity environments and differentiates between solid particulates and liquid aerosols.

laser scattering, particulate counter, sensor technology, environmental compensation

Patent

Enhanced conductor interconnects

Patent published on the 2026-10-15 in US under Ref US20260324392 by INT BUSINESS MACHINES CORPORATION [US] (Chen Ching-tzu [us], Gluschenkov Oleg [us], Nguyen Son [us], Lavoie Christian [us])

Abstract: [0000] A semiconductor device includes a vertical interconnect having an enhanced conductor. A buffer layer is disposed between the enhanced conductor and a dielectric material. The enhanced conductor and the buffer layer include vertically disposed interfaces with surface-state conductive paths along the interfaces.[...]


Our summary: A semiconductor device features a vertical interconnect with an enhanced conductor. A buffer layer is placed between the enhanced conductor and a dielectric material. The interfaces of the enhanced conductor and buffer layer provide surface-state conductive paths.

vertical interconnects, enhanced conductor, buffer layer, semiconductor device

Patent

Vaporizing system

Patent published on the 2026-10-15 in US under Ref US20260324338 by MERCK PATENT GMBH [DE] (Cho Jae-seoung [kr])

Abstract: [0000] A semiconductor manufacturing vaporizing system is disclosed. The system may comprise a first-gas-conduit, a buffer tank positioned upstream of and fluidly coupled to the first-gas-conduit configured to store a first material in a gaseous state at a first pressure, and a second-gas-conduit upstream of and fluidly coupled to the buffer tank configured to convey a gas-stream to the buffer tank. The system may also include a vaporizer upstream of and fluidly coupled to the second-gas-conduit[...]


Our summary: The semiconductor manufacturing vaporizing system includes a buffer tank for storing gas at a specific pressure. It features a vaporizer that induces a phase change of the first material. Additionally, a pump propels a non-pressurized liquid stream to the vaporizer through a liquid conduit.

vaporizing system, semiconductor manufacturing, gas-conduit, phase change

Patent

Semiconductor device and methods of formation

Patent published on the 2026-10-15 in US under Ref US20260324402 by TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD [TW] (Chang Wei-jen [tw], Jiang Jheng-yi [tw], Hsu Ruei-jyun [tw], Ho Chia-chi [tw], Chiang Chung-shih [tw])

Abstract: [0000] A semiconductor transistor device includes gate electrodes on a first side (e.g., frontside) of the device and source/drain electrodes disposed in recesses formed from a second side (e.g., backside) of the device. The recesses are formed from the backside of the device through a substrate and into a gallium-based layer. The recesses are filled with conductive (e.g., metal) material to form the source/drain electrodes. The source/drain electrodes may be formed in part of the gallium-based [...]


Our summary: A semiconductor transistor device features gate electrodes on the frontside and source/drain electrodes in recesses from the backside. The recesses are filled with conductive material and may connect to a backside ground plate for heat dissipation. This configuration allows for reduced width, enhancing electron mobility and lowering serial resistance.

semiconductor, transistor, source/drain electrodes, gallium-based layer

Patent

Light-emitting diode displays with low latency and related methods

Patent published on the 2026-10-15 in US under Ref US20260323801 by CREELED INC [US] (Hussell Christopher P [us])

Abstract: [0000] Light-emitting diode (LED) packages and, more particularly, LED displays with low latency and related methods are disclosed. LED displays and related methods include reverse-pixel addressing that involves arranging data stream segments in reverse order so that an LED package that is farthest away in a serial string receives its data segment precedently or concurrently with that of an LED package positioned at the beginning of the serial string. LED packages form LED pixels of an array whe[...]


Our summary: LED displays utilize low latency techniques through reverse-pixel addressing. This method allows data segments to be arranged in reverse order for efficient data loading. The result is that all LED pixels receive their data simultaneously, enabling quick frame advancement.

LED displays, low latency, reverse-pixel addressing, data stream segments

Patent

Bonded cold plate with lateral compliance

Patent published on the 2026-10-15 in US under Ref US20260324425 by ERIDU CORP [US] (Ice Donald Arthur [us], Ch Ting-kuang [us])

Abstract: [0000] Some implementations described herein provide a cold plate for semiconductor cooling that incorporates structural compliance to accommodate differential thermal expansion between the cold plate and adjacent semiconductor chips. For example, the apparatus includes a cold plate comprising a first portion with a plurality of thermally conductive portions, such as pillars, wherein the pillars are spaced from one another at their first ends adjacent the chip surface. The cold plate is configur[...]


Our summary: The cold plate is designed for semiconductor cooling with structural compliance to accommodate thermal expansion. It features thermally conductive pillars that absorb stress in the X and Y directions while maintaining rigidity in the Z direction. The design may include compliant ribs and channels for coolant flow, enhancing heat transfer from the semiconductor chips.

cold plate, thermal expansion, semiconductor cooling, structural compliance

Patent

Theory of spin qubits and the path to scalability

Published on 2026-08-21 by Z M McIntyre, Abhikbrata Sarkar and Daniel Loss @IOP SCIENCE

Abstract: Spin qubits have emerged as a leading platform for quantum information processing due to their long coherence times, small footprint, and compatibility with the existing semiconductor industry. We first provide an introduction to the different qubit implementations currently being investigated, including single electron-spin qubits, hole-spin qubits, donor qubits, and multispin encodings. We discuss how the confinement and strain present in semiconductor heterostructures produce addressable leve[...]


Our summary: Spin qubits are a promising platform for quantum information processing due to their long coherence times and small footprint. The paper reviews various qubit implementations and the effects of confinement and strain in semiconductor heterostructures. It also discusses mechanisms for long-range coupling and a proposal for linking spin qubits using topological spin textures.

spin qubits, quantum information processing, semiconductor heterostructures, long-range coupling

Publication

Material-specific lighting requirements and contemporary illumination strategies for galleries

Published on 2026-07-08 by @OXFORD

Abstract: AbstractMuseum lighting simultaneously governs visual presentation and light-induced degradation of artworks. With the widespread adoption of light emitting diode technologies, traditional illuminance- and dose-based standards are increasingly insufficient to address the heterogeneous photochemical responses of different materials. This review synthesizes recent research on material-specific lighting requirements and contemporary illumination strategies for galleries, focusing on spectral power [...]


Our summary: This review addresses material-specific lighting needs and modern strategies for gallery illumination. It highlights the varying sensitivity of artworks to different light wavelengths and the impact on visual presentation and degradation. Optimized lighting approaches can significantly enhance energy efficiency while preserving artwork integrity.

museum lighting, photochemical responses, illumination strategies, energy optimization

Publication

Temas tratados: semiconductores, diodo, MOFSET, unión PN, tipo N, tipo P, BJT, JFET, unión Schottky, crecimiento ALD, baterías de iones de litio, semiconductores tipo p de alta movilidad, diodo Josephson, disulfuro de molibdeno, nanomateriales, propiedades electroquímicas, método hidrotermal, fotodetección, ISO 9001, IEC 60747, IEEE 8023, IEC 61215 e ISO 14001.

Contexto histórico

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(Si la fecha es desconocida o no es relevante, por ejemplo "mecánica de fluidos", se proporciona una estimación redondeada de su aparición notable)

décimo año aniversario

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