Últimas publicaciones y patentes sobre FPGA

FPGA

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This is our latest selection of worldwide publications and patents in english on FPGA, between many scientific online journals, classified and focused on FPGA, logic block, programmable interconnect, I/O block, IP core, hard IP, soft IP, look-up table, DSP, digital signal processing, system on a chip, high-level synthesis, field-programmable analog array and FPAA.

A High-Entropy True Random Number Generator with Keccak Conditioning for FPGA

Published on 2025-03-08 by Valeria Piscopo, Alessandra Dolmeta, Mattia Mirigaldi, Maurizio Martina, Guido Masera @MDPI

Abstract: Any cryptographic system strongly relies on randomness to ensure robust encryption and masking methods. True Random Number Generators play a fundamental role in this context. The National Institute of Standards and Technology (NIST) and the Bundesamt für Sicherheit in der Informationstechnik (BSI) provide guidelines for designing reliable entropy sources to fuel cryptographic Random Bit Generators. This work presents a highly parameterized, open-source implementation of a TRNG based[...]


Our summary: Implementation of a highly parameterized TRNG with optimized Keccak conditioning unit, meeting NIST and BSI guidelines, achieving high min-entropy per bit.

True Random Number Generator, High-Entropy, Keccak Conditioning, FPGA

Publication

Research on Approximate Computation of Signal Processing Algorithms for AIoT Processors Based on Deep Learning

Published on 2025-03-07 by Yingzhe Liu, Fangfa Fu, Xuejian Sun @MDPI

Abstract: In the post-Moore era, the excessive amount of information brings great challenges to the performance of computing systems. To cope with these challenges, approximate computation has developed rapidly, which enhances the system performance with minor degradation in accuracy. In this paper, we investigate the utilization of an Artificial Intelligence of Things (AIoT) processor for approximate computing. Firstly, we employed neural architecture search (NAS) to acquire the neural network structure [...]


Our summary: Research investigates approximate computation of signal processing algorithms for AIoT processors based on deep learning. Neural architecture search is employed to acquire the neural network structure for approximate computation, which approximates functions of FFT, DCT, FIR, and IIR. Performance evaluation shows significantly higher computational efficiency on AI accelerator compared to traditional DSP implementations.

Approximate Computation, Signal Processing Algorithms, AIoT Processors, Deep Learning

Publication

Accelerating Pattern Recognition with a High-Precision Hardware Divider Using Binary Logarithms and Regional Error Corrections

Published on 2025-03-07 by Dat Ngo, Suhun Ahn, Jeonghyeon Son, Bongsoon Kang @MDPI

Abstract: Pattern recognition applications involve extensive arithmetic operations, including additions, multiplications, and divisions. When implemented on resource-constrained edge devices, these operations demand dedicated hardware, with division being the most complex. Conventional hardware dividers, however, incur substantial overhead in terms of resource consumption and latency. To address these limitations, we employ binary logarithms with regional error correction to approximate division operation[...]


Our summary: Accelerating pattern recognition with a high-precision hardware divider using binary logarithms and regional error corrections, reducing hardware complexity and minimizing errors, implemented on a Zynq UltraScale+ FPGA platform.

Pattern Recognition, High-Precision Hardware Divider, Binary Logarithms, Regional Error Corrections

Publication

Hardware Acceleration-Based Privacy-Aware Authentication Scheme for Internet of Vehicles Using Physical Unclonable Function

Published on 2025-03-06 by Ujunwa Madububa Mbachu, Rabeea Fatima, Ahmed Sherif, Elbert Dockery, Mohamed Mahmoud, Maazen Alsabaan, Kasem Khalil @MDPI

Abstract: Due to technological advancement, the advent of smart cities has facilitated the deployment of advanced urban management systems. This integration has been made possible through the Internet of Vehicles (IoV), a foundational technology. By connecting smart cities with vehicles, the IoV enhances the safety and efficiency of transportation. This interconnected system facilitates wireless communication among vehicles, enabling the exchange of crucial traffic information. However, this significant t[...]


Our summary: Innovative privacy-preserving authentication scheme for IoV using PUFs and hardware acceleration. Two-layer security approach against cyber-attacks. Performance analysis shows minimal communication and computational burden.

Hardware Acceleration, Privacy-Preserving Authentication, Internet of Vehicles, Physical Unclonable Function

Publication

Semiconductor device with redacted logic

Patent published on the 2025-03-06 in WO under Ref WO2025049173 by BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC [US] (Moser David [us], Stanley Daniel [us], Gilliam Jane [us])

Abstract: A semiconductor device includes a data port, a programmable logic block for executing a manufacturer test, and a processor operatively coupled to the data port. The processor is configured to assert, in a first modality, a configuration isolation signal to the data port. The data port is configured to be communicatively isolated from the programmable logic block while the configuration isolation signal is asserted. The processor is configured to de-assert, in a second modality, the configuration[...]


Our summary: Redacted logic in semiconductor device, configuration isolation signal control, communication interface data loading from FIFO buffer

semiconductor device, programmable logic block, data port, processor

Patent

Predicted bias correction for drilling fluids

Patent published on the 2025-03-06 in WO under Ref WO2025048854 by HALLIBURTON ENERGY SERVICES INC [US] (Rowe Mathew Dennis [us], Kevadiya Jhanvi Manishkumar [us])

Abstract: A system can displace a headspace associated with a drilling fluid sample with a hydrocarbon blend with a first volume a hydrocarbon gas. The system can also extract the hydrocarbon blend from the head space associated with the drilling fluid sample. The system can further determine a concentration over time of the hydrocarbon gas of the hydrocarbon blend and generating a gas decay curve of the concentration over time of the hydrocarbon gas. Additionally, the system can determine, based on the g[...]


Our summary: Predicted bias correction for drilling fluids using a system to displace headspace with a hydrocarbon blend, extract the blend, determine gas concentration over time, and correct bias with an extraction efficiency correction factor.

bias correction, drilling fluids, hydrocarbon blend, gas extraction

Patent

Radiation-hardened field-programmable gate arrays

Patent published on the 2025-03-06 in WO under Ref WO2025048765 by CARNEGIE MELLON UNIV [US] (Mai Kenneth W [us], Kibar Ogun Onur [us], Mohan Prashanth [us], Atli Ahmet Oguz [us])

Abstract: Disclosed herein is a novel system and method for detecting, localizing, and correcting configuration upsets of an SRAM-based FPGA design caused by radiation exposure. The radiation-hardened FPGA uses embedded strike sensors distributed throughout the FPGA fabric, coupled with an error handler to correct the upsets using a redundant on-chip copy of the configuration.[...]


Our summary: Novel system for detecting, localizing, and correcting configuration upsets caused by radiation exposure using embedded strike sensors and error handler with redundant on-chip configuration copy.

Radiation-hardened, field-programmable gate arrays, SRAM-based FPGA design, configuration upsets

Patent

Dynamic sole protrusions for cleated footwear

Patent published on the 2025-03-06 in WO under Ref WO2025049414 by BARNES BROOKS [US] (Barnes Brooks [us])

Abstract: Embodiments of the instant disclosure provide dynamic sole protrusions (DSPs) and shoe soles that contain the same. The shoe sole includes a plurality of DSPs as well as a sole surface having a heel region and a forefoot region. The sole surface includes a first polymeric material. Each DSP includes a second polymeric material, is affixed to and extends from the heel region, as well as is substantially oriented perpendicular to the sole surface. Each DSP longitudinally flexes when a predetermine[...]


Our summary: Shoe sole with dynamic sole protrusions allows for lateral movement of heel region, DSPs positioned in V-shape near medial line, each DSP flexes with longitudinal force.

dynamic sole protrusions, cleated footwear, polymeric material, longitudinal flexes

Patent

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    Temas tratados: FPGA, bloque lógico, interconexión programable, bloque de E/S, núcleo IP, IP dura, IP blanda, tabla de consulta, DSP, procesamiento digital de señales, sistema en un chip, síntesis de alto nivel, matriz analógica programable en campo, generador real de números aleatorios, cálculo aproximado, inteligencia artificial de las cosas, reconocimiento de patrones, autenticación que preserva la privacidad

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