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최신 논문 – 뉴로모픽 컴퓨팅 관련 특허

Publications & Patents on Neuromorphic Computing

팁: 아래 선택 항목 외에도, 저희가 제공하는 두 개의 전체 데이터베이스를 검색하고 필터링할 수 있습니다.

> 무료 간행물 검색 도구 < 저자, 주제, 키워드, 날짜 또는 저널별로 검색.

> 무료 특허 검색 도구 < 유럽 ​​특허청의 영문 특허를 참조하십시오.

뉴로모픽 컴퓨팅은 생물학적 신경망, 특히 인간의 뇌의 구조와 기능에서 영감을 받아 하드웨어 및 소프트웨어 시스템을 설계하는 학제 간 분야입니다. 프로세서와 메모리가 긴밀하게 통합된 비폰 노이만 아키텍처를 사용하여 대규모 병렬 연산, 이벤트 기반 정보 처리, 저전력 작동을 가능하게 합니다. 인공 스파이크 뉴런과 시냅스 같은 요소를 활용하여 뉴로모픽 시스템은 학습, 적응, 감각 처리 등 뇌의 메커니즘을 모방합니다.

본 자료는 신경모방 컴퓨팅, 스파이킹 신경망, 누설 적분-발화 뉴런, 멤리스터, 신경모방, 시냅스 가소성, 축삭 지연, 실리콘 뉴런, 아날로그 VLSI, 헤비안 학습 및 스파이킹 신경망을 주제로 분류하고 집중적으로 다룬 전 세계 영문 논문 및 특허를 엄선하여 정리한 온라인 과학 저널 목록입니다.

Photonic array, methods of forming or operating the same

Patent published on the 2026-10-01 in WO under Ref WO2026206249 by UNIV NANYANG TECH [SG] (Jiang Wenyu [sg], Wang Qian [sg], Liu Zheng [sg], Sia Jia Xu Brian [sg], Wang Yixin [sg], Liu Hong [sg], Wang Qijie [sg], B J Sajay [sg], Wang Hong [sg])

Abstract: Various embodiments may relate to a photonic array. The photonic array may include a plurality of synapses arranged in a M × N matrix, where M represents a number of rows and N represents a number of columns. Each of the plurality of synapses may include an optical resonator and a photonic memristor coupled to the optical resonator. The photonic array may be configured such that only one column of the photonic array is selected at a time for programming via a suitable means. The photonic array [...]


Our summary: The photonic array consists of a matrix of synapses with optical resonators and photonic memristors. It allows programming of a selected column using specific optical pulses for each row. During inference, equal optical power flows through all synapses.

Photonic array, synapses, optical resonator, photonic memristor

Patent

systems and methods for high-efficiency computing leveraging recognition physics principles

Patent published on the 2026-09-24 in US under Ref US20260288676 by WASHBURN JONATHAN [US] (Washburn Jonathan [us])

Abstract: Systems, methods, apparatus, and non-transitory computer-readable media are disclosed for recognition-based computing control. In some embodiments, one or more metrics associated with one or more computational entities or runtime conditions are normalized to obtain one or more dimensionless recognition metrics. One or more recognition coverage values are computed according to F_cov(r)=r/(r+X_opt), where r is a dimensionless recognition metric and X_opt is a positive informational scale. One or m[...]


Our summary: This document describes systems and methods for high-efficiency computing using recognition physics principles. It details the normalization of metrics related to computational entities to derive dimensionless recognition metrics. The generated recognition coverage values are utilized to control various computing subsystems, including task scheduling and resource allocation.

high-efficiency computing, recognition physics, computational entities, machine-control outputs

Patent

A computer-implemented method for occupancy detection of a space

Patent published on the 2026-09-24 in WO under Ref WO2026195908 by INNATERA NANOSYSTEMS B V [NL] (Nagy Sebastian Eusebiu [nl], Toma Vasile [nl], Eissa Sherif Salahaldeen Badawy [nl])

Abstract: The present disclosure relates to a computer-implemented method for occupancy detection of a space. The method comprising, acquiring thermal image data comprising a sequence of thermal image frames of the space with a thermal imaging device, providing an occupancy detection unit comprising a spike-encoder and a spiking neural network (SNN). The SNN is partially or fully implemented in hardware and trained to determine an occupancy parameter based on one or more thermal image frames. The method f[...]


Our summary: The method utilizes thermal image data to detect occupancy in a space. It employs a spiking neural network trained to analyze thermal frames. The occupancy detection module processes the encoded thermal frames to determine occupancy parameters.

occupancy detection, thermal imaging, spiking neural network, spike-encoder

Patent

Solar cell unit comprising a solar cell and a memristor and photovoltaic module

Patent published on the 2026-09-23 in EP under Ref EP4811984 by ZHAW ZUERCHER HOCHSCHULE FUER ANGEWANDTE WSS [CH] (Tress Wolfgang [ch], Mohammadi Mahdi [ch])

Abstract: [0001] The present invention relates to a solar cell unit (S1) comprising at least a solar cell (Sc1) and at least a memristor (M1). The memristor (M1) is connected in parallel to the solar cell (Sc1). Furthermore, the invention relates to a photovoltaic module (P) with a string of solar cell units.[...]


Our summary: The invention describes a solar cell unit that includes a solar cell and a memristor connected in parallel. It also details a photovoltaic module consisting of multiple solar cell units. This configuration aims to enhance the efficiency of solar energy conversion.

solar cell, memristor, photovoltaic module, parallel connection

Patent

High signal-to-noise-ratio memory cell programming for in-memory computing

Patent published on the 2026-09-02 in EP under Ref EP4800691 by OMNIVISION TECH INC [US] (Saito Daisuke [us])

Abstract: An in-memory computing system includes a cross-bar array (414, 514) of memory cells, each having a cell transistor and a memristor connected in series between a select line and a bit line. A group of programming transistors, located outside the cross-bar array and fewer in number than the memory cells, is selectively connected in parallel with cell transistors of a common row during a write mode and isolated during a read mode. This configuration increases programming current without enlarging a[...]


Our summary: The in-memory computing system utilizes a cross-bar array of memory cells with a series connection of a cell transistor and a memristor. It features programming transistors that enhance current during write operations while minimizing space requirements. This design allows for multi-level conductance states and improved signal-to-noise ratios, facilitating on-sensor inference with integrated image sensors.

in-memory computing, memory cell programming, signal-to-noise ratio, memristor

Patent

current status, progress and opportunities in machine learning for Earth system observation and prediction

Published on 2026-08-31 by Massimo Bonavita, Rochelle Schneider, Mounia El Baz, Rossella Arcucci, Marc Bocquet, Marcin Chrust, Maryam Pourshamsi, Chiara Maria Cocchiara, Alberto Carrassi, Nina Raoult, Diego Jatob Dos Santos @NATURE npj

Abstract: npj Climate and Atmospheric Science, Published online: 31 August 2026; doi:10.1038/s41612-026-01486-6The 5th ECMWF-ESA Machine Learning Workshop (Bologna, Italy; 13-17 April 2026) convened the Earth System Observation and Prediction (ESOP) community to assess progress and new directions in the general field of the application of Machine Learning to ESOP and the specific thematic areas of Machine Learning (ML) for Digital Twins, hybrid ML-physics systems, ML for Earth observation (EO), end-to-end[...]


Our summary: The workshop assessed progress and future directions in applying machine learning to Earth system observation and prediction. It highlighted advancements in ML for digital twins, hybrid systems, and end-to-end workflows. The event showcased a shift towards GPU/TPU-centric computing and emerging paradigms like quantum and neuromorphic computing.

Machine Learning, Earth Observation, Data Assimilation, High-Performance Computing

Publication

Analog in-memory computing device for neural network

Patent published on the 2026-08-26 in EP under Ref EP4797264 by OMNIVISION TECH INC [US] (Saito Daisuke [us])

Abstract: [0001] An analog in-memory computing device for a neural network is provided. The analog in-memory computing device includes a memristor array and a readout circuit. The readout circuit includes a differential amplifier circuit (AMP3, AMP4, AMP5, AMP6) and a plurality of current-voltage conversion circuits (CVC31 to CVC3n, CVC41 to CVC4n, CVC51 to CVC5n, CVC61 to CVC6n). A first input terminal of the differential amplifier circuit (AMP3, AMP4, AMP5, AMP6) is coupled to a reference voltage source[...]


Our summary: The device features a memristor array and a readout circuit for neural networks. It includes a differential amplifier and multiple current-voltage conversion circuits. The readout circuit outputs voltage results corresponding to the memristor array s column lines.

memristor, neural network, analog computing, readout circuit

Patent

Reconfigurable ferroelectric chiral nanostructures enable fast-switchable optical spatial differentiation

Published on 2026-06-26 by Wen Chen, Dong Zhu, Su-Nan Chen, Yi-Heng Zhang, Si-Jia Liu, Rui Sun, Yi-Ming Wang, Lin Zhu, Shi-Hui Ding, Shi-Jun Ge, Yan-Qing Lu, Peng Chen @NATURE

Abstract: Light: Science & Applications, Published online: 26 June 2026; doi:10.1038/s41377-026-02363-wWe propose a reconfigurable space-variant ferroelectric chiral nanostructure to dynamically control the optical differentiation. Via switching the polarity of external electric field, spatial differentiation or bright-field imaging can be actively selected with an ultra-short response time. This work advances the ingenious building of ferroelectric nanostructures, and offers an important glimpse into[...]


Our summary: Reconfigurable ferroelectric chiral nanostructures allow for dynamic control of optical differentiation. The polarity of an external electric field enables active selection of spatial differentiation with ultra-short response times. This research highlights the potential applications in neuromorphic photonics, biomedical microscopy, and artificial intelligence.

reconfigurable nanostructures, ferroelectric materials, optical differentiation, neuromorphic photonics

Publication

다룬 주제: 뉴로모픽 컴퓨팅, 스파이킹 신경망, 누설 적분발화 뉴런, 멤리스터, 시냅스 가소성, 축삭 지연, 실리콘 뉴런, 아날로그 VLSI, 헤비안 학습, 비폰 노이만 아키텍처, 이벤트 기반 정보 처리, 대규모 병렬 컴퓨팅, ISO/IEC 30170, IEEE 802154, IEC 61966-2-1, ISO/IEC 24765 및 ISO 26262.

역사적 맥락

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(날짜를 알 수 없거나 관련이 없는 경우, 예를 들어 "유체역학"의 경우, 주목할 만한 등장 시기를 대략적으로 추정하여 제공합니다.)

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