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Ultime pubblicazioni e brevetti su FPGA

FPGA

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Questa è la nostra ultima selezione di pubblicazioni e brevetti in inglese su FPGA, tra numerose riviste scientifiche online, classificate e incentrate su FPGA, blocco logico, interconnessione programmabile, blocco I/O, nucleo IP, hard IP, soft IP, look-up table, DSP, elaborazione del segnale digitale, system on a chip, sintesi di alto livello, field-programmable analog array e FPAA.

Audio system and method for providing saturation on audio output

Patent published on the 2026-10-15 in US under Ref US20260323211 by HARMAN BECKER AUTOMOTIVE SYSTEMS INC [US] (Daftuar Rishi [us], Porter James Mccallister [us], Humphrey Stephen Michael [us])

Abstract: [0000] An audio system includes an amplifier including at least one controller and being programmed to receive an audio input signal; apply saturation to at least the audio input signal by introducing non-linear distortion to provide an audio output signal; and transmit an audio output signal to one or more loudspeakers to playback the audio out of a first loudspeaker of the one or more loudspeakers.[...]


Our summary: The audio system applies saturation by introducing non-linear distortion to the audio input signal. It includes an amplifier with a controller programmed for this purpose. The processed audio output is transmitted to loudspeakers for playback.

saturation, audio output, amplifier, non-linear distortion

Patent

Systems and methods for control of arbitrary-precision numbers in high-level synthesis

Patent published on the 2026-10-08 in US under Ref US20260310579 by MICROSEMI SOC CORP [US] (Saldana De Fuentes Manuel Alejandro [ca], El-sheikha Hassan [ca])

Abstract: [0000] Techniques are disclosed for runtime analysis of numerical assignments in a high-level synthesis (HLS) environment. Source code and a user-supplied test vector are compiled with a verification library that overloads an operator for a numerical variable that stores a result. The compiling includes inserting code that, for each overloaded operator, redirects the store to a runtime routine, the redirecting being an assignment operation. During execution, the runtime routine evaluates the rig[...]


Our summary: Techniques for controlling arbitrary-precision numbers in high-level synthesis are disclosed. The method includes runtime analysis of numerical assignments and logging overflow quantization errors. After execution, the system recommends or automatically corrects bit widths to address detected issues.

arbitrary-precision, high-level synthesis, runtime analysis, bit width modification

Patent

Crowd-sourced curation and training of ai models for karaoke-style performances

Patent published on the 2026-10-01 in US under Ref US20260301763 by SMULE INC [US] (Smith Jeffrey C [us], Boyanov Martin [bg], Leistikow Randal J [us], Cook Perry R [us], Zang Yongyi [us])

Abstract: Digital signal processing and artificial intelligence (AI)-based techniques can be employed in a vocal capture and performance social network to computationally train AI models using vocal audio performances sourced from one or more performers and captured at respective vocal capture devices or platforms. In particular, the AI models may be trained using a curated set of the vocal audio performances, where the curated set is selected based on correspondence with computationally-derived features,[...]


Our summary: The content discusses using crowd-sourced vocal audio performances to train AI models for karaoke-style applications. It highlights the role of digital signal processing in capturing and curating vocal performances. The trained models can transform subsequent vocal captures to match a target performance style.

AI training, vocal capture, digital signal processing, karaoke performances

Patent

Uncorrectable error correction code (uecc) marking of l2p mapping units

Patent published on the 2026-10-01 in US under Ref US20260300065 by SANDISK TECHNOLOGIES INC [US] (Booth Jing Shi [us], Inbar Karin [il], Yonin Michael Micha [il], Gorrle Dhanunjaya Rao [us])

Abstract: Use of a partial L2P mapping scheme improves costs and uncorrectable byte error rates in large sized SSD when mapping granularity is greater than the basic read unit in NAND. In a L2P table, a mega-fixed logic block address (mFFLBA) may map to a cluster of consecutive FMUs, numbered by JBAs. By special marking in the NAND only the jumbo block addresses (JBAs) in the cluster that have an uncorrectable error, the storage device can avoid mark the all the JBAs associated with the mFFLBA as uncorrec[...]


Our summary: The use of a partial L2P mapping scheme enhances cost efficiency and reduces uncorrectable byte error rates in large SSDs. By marking only the JBAs with uncorrectable errors, the system preserves non-corrupt data within the same cluster. This approach improves overall storage device reliability by lowering defective parts per million (DPPM).

Uncorrectable error correction, L2P mapping, SSD reliability, NAND storage

Patent

Loudspeaker control in a plurality of frequency bands

Patent published on the 2026-09-30 in EP under Ref EP4815512 by AUDIOSCENIC LTD [GB] (Ushakov Yury [gb], Carvalho Davi [gb], Hollebon Jacob [gb], SimÓn Marcos [gb], Wallace Daniel [gb])

Abstract: [0001] A computer-implemented method of generating audio signals for an array of loudspeakers in a plurality of frequency bands is provided, and comprises: obtaining the plurality of frequency bands; receiving a plurality of input audio signals to be reproduced, by the array, in an acoustic environment, wherein each of the plurality of input audio signals comprises a sub-signal in each of the plurality of frequency bands, and wherein each of the sub-signals in at least one of the plurality of fr[...]


Our summary: The method generates audio signals for loudspeakers across multiple frequency bands. It involves obtaining input audio signals and position information for control points. An SFC mode is selected for each frequency band to apply an SFC algorithm to the corresponding sub-signals.

Loudspeaker control, frequency bands, audio signals, sound field control

Patent

Multiple core processor for efficient inference of machine learning workloads

Patent published on the 2026-09-30 in EP under Ref EP4814728 by INTEL CORP [US] (Gaur Jayesh [in], Ranganathan Adithya [in], Balachandran Shankar [in], Mahto Sujit [in], Shukla Sudhanshu [in], Subramoney Sreenivas [in], Shifer Eran [il])

Abstract: [0001] A multiple core processor for efficient inference of machine learning workloads is described. In certain examples, a computing system (e.g., system on a chip) includes a system memory; a cache; a plurality of processor cores; an interconnect; a plurality of cache coherence circuits to manage access on the interconnect between the plurality of processor cores, the cache, and the system memory; and a power management circuit to cause a switch from a first mode that configures the plurality [...]


Our summary: A multiple core processor enhances the efficiency of machine learning workloads. It features a system memory, cache, and multiple processor cores connected via an interconnect. The design includes power management for dynamic reconfiguration to optimize output generation from machine learning models.

multiple core processor, efficient inference, machine learning, cache coherence

Patent

A Real&ndash;Virtual Fusion Approach with Inconsistency Mitigation

Published on 2026-02-03 by Sukwoo Jung, Myeongseop Kim, Jean Oh, Jonghwa Kim, Kyung-Taek Lee @MDPI

Abstract: Autonomous driving systems rely on vast and diverse datasets for robust object recognition. However, acquiring real-world data, especially for rare and hazardous scenarios, is prohibitively expensive and risky. While purely synthetic data offers flexibility, it often suffers from a significant reality gap due to discrepancies in visual fidelity and physics. To address these challenges, this paper proposes a novel real&amp;ndash;virtual fusion framework for efficiently generating highly reali[...]


Our summary: This paper presents a real-virtual fusion framework for generating realistic augmented datasets for autonomous driving. It synchronizes real-world data with a digital twin environment to inject virtual objects into real images. The approach focuses on inconsistency mitigation to enhance visual fidelity and improve perception model generalization.

real-virtual fusion, autonomous driving, dataset generation, inconsistency mitigation

Publication

FPGA-Based Real-Time Measurement System for Single-Shot Carrier-Envelope Phase in High-Repetition-Rate Laser Amplification Systems

Published on 2026-02-03 by Wenjun Shu, Pengfei Yang, Wei Wang, Xiaochen Li, Nan Wang, Zhen Yang, Xindong Liang @MDPI

Abstract: To address the issue of low closed-loop feedback bandwidth caused by the long latency of Carrier-Envelope Phase (CEP) measurement systems for amplified femtosecond laser pulses, and to meet the requirements for real-time single-shot measurement in 10 kHz repetition rate systems, this paper proposes a microsecond-level low-latency CEP measurement technique based on a Field-Programmable Gate Array (FPGA). To tackle the problem of non-uniform spectral sampling resulting from nonlinear wavelength-fr[...]


Our summary: This paper presents a low-latency CEP measurement technique using FPGA for 10 kHz laser systems. It employs a real-time linear interpolation algorithm to address non-uniform spectral sampling issues. The system achieves a processing latency of approximately 89 µs, significantly improving measurement accuracy.

FPGA, Carrier-Envelope Phase, real-time measurement, laser amplification

Publication

Argomenti trattati: FPGA, blocco logico, interconnessione programmabile, blocco I/O, core IP, hard IP, soft IP, tabella di look-up, DSP, elaborazione del segnale digitale, system on a chip, sintesi ad alto livello, array analogico programmabile in campo, SRAM-based FPGA resistente alle radiazioni, upsets di configurazione, sporgenze dinamiche della suola e celle fotovoltaiche bifacciali....

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